1. Field of the Invention
A method of manufacturing a TFT panel, and more particularly, to a method of manufacturing a LTPS TFT OLED panel.
2. Description of the Prior Art
In general, low temperature poly crystalline silicon thin film transistor (LTPS TFT) array manufacturing needs about six to nine photo-masks to process a photolithograph etching process (PEP), which is more complex than five photo-masks required to manufacture the hydrogenated amorphous silicon thin film transistor (α-Si:H TFT). In addition, the active matrix organic light-emitting diode (AMOLED) needs seven to ten photo-masks, because of the need to manufacture an LTPS TFT array and a pixel define layer (PDL).
Please refer to FIG. 1. FIG. 1 is schematic diagram of a traditional OLED TFT structure 100. In the prior art, a glass substructure 102 is provided, with an insulator layer 104 and amorphous silicon film (not shown) doped on the glass substructure 102. The amorphous silicon film then re-crystallizes to polycrystalline silicon after an excimer laser annealing (ELA) process. Then, an active layer 106 pattern is etched on the polycrystalline silicon by a first PEP with a first mask, and a gate insulator layer 108 is deposited on the active layer 106 and the insulator layer 104.
Moreover, a gate metal 110 is etched by a metal etching process, a second mask, and a second PEP. The gate metal 110 is a self-alignment mask and the boron ion doping process proceeds on the active layer 106, forming a source 103 and a drain 105 on the corresponding sides of the gate metal 110. In the prior art, a capacitance (Cst) 113 is formed on a poly silicon lower panel 107, the gate insulator layer 108 and a gate metal upper panel 111 by the above-mentioned first PEP and the second PEP individually. Then, an inter-layer dielectric (ILD) 112 is doped on the glass substructure 102 to cover the gate metal 110, the gate metal upper panel 111, and the gate insulator layer 108. The particle ILD and the gate insulator layer 108 of the source 103 and the drain 105 are then removed by a third photo-mask and a third PEP to define a corresponding via hole 115. Furthermore, a metal etching process is performed utilizing a fourth photo-mask, and the fourth mask etches a data line and a drain metal on the via hole 115 of metal layer 114 for electrically contacting the source 103 and the drain 105. A flat passivation layer 116 is doped on the metal layer 114 and the ILD 112 using a fifth photo-mask and a fifth PEP, and the passivation layer 116 on the metal layer 114 which electrically contacts the drain 105 is removed. An ITO transparent electrode film (not shown) is formed on the passivation layer 116, and a sixth photo-mask and a sixth PEP are used to define the suitable shape of the transparent electrode 118. Then, a pixel define layer (PDL) 120 is processed and is etched by a seven photo-mask and a seven PEP. Finally, a LED (not shown) is formed on the transparent electrode 118 to complete the traditional OLED panel 110.
In the prior art, seven photo-masks are needed to complete the above-mentioned OLED. The process is complex and the use of too many masks increases the cost and increases the misalignment, thereby decreasing the yield. That is why decreasing the number of the photo-masks is an important issue in the monitor manufacturing industry.